Digital systems employing certain logic circuits take advantage of the functional completeness of the NAND, i.e., any logic function (AND, OR, etc.) can be implemented using NAND and NOR gates More specifically, an NAND gate is a digital logic gate that behaves in a particular manner. For example, a low output results only if both the inputs to the gate are high. However, if one or both inputs are low, a high output results. NAND gates can also be made with more than two inputs, yielding an output of low if all of the inputs are high, and an output of high if any of the inputs is low. These kinds of gates therefore operate as n-ary operators instead of a simple binary operator.
In conventional systems, a NAND gate includes a stacked configuration of two asymmetric FETs in series. The asymmetric FETs provide the advantage of low source external resistance, reduced floating body voltages and reduced drain-gate and drain-body capacitance during the saturation mode. Thus, advantageously, NAND circuits gain the advantage of the saturated current drive capabilities and low Miller capacitance of the asymmetric FET.
However, in the linear mode of operation, the voltage across the drain source becomes small thus making the device susceptible to weak overlap on the drain side. The weak drain overlap has a negligible impact on the saturated current drive; however, it has a significant impact on the linear current degradation in the linear mode. That is, the weak drain overlap leads to high drain external resistance that degrades Idlin. In turn, the Idlin degradation decreases the benefit of using the asymmetric NFETs in stacked NFET circuits.
More specifically, the stack (i.e., asymmetric NFETs) is highly susceptible when the top circuit is switched, as the stack is sensitive to the linear current drive of the devices at the bottom of the stack. Thus, the weak current overlap of the asymmetric NFETs leads to linear current degradation in the bottom of the device which has a significant impact on performance. Thus, although saturation current goes way up, the linear current degradation in the linear mode goes way down which will affect device performance. So, by using an asymmetric NFET at the bottom of the stack, the performance of the NFET is affected by the linear current degradation in the linear mode.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.